The GD32VF103 This chip is a peripheral clone of an STM32F103. The CPU is swapped out for a Risc-V. Openocd debug using JTAG Using the release on github: https://github.com/riscv/riscv-openocd Build it: ./bootstrap ./configure --enable-ftdi --enable-stlink --enable-ti-icdi --enable-jlink --enable-cmsis-dap --enable-xds110 make We can connect to the target. Wiring to a J-Link is as so: ARM20 JTAG: Pin1 VCC -> 3V3 Pin3 TRST -> RESET Pin5 TDI -> JTDI (underside of board) Pin7 TMS -> JTMS Pin9 TCLK -> JTCLK Pin13 TDO -> JTDO Add this to openocd/tcl/board as bluepillGDF103.cfg adapter speed 8000 source [find interface/jlink.cfg] source [find target/longan.cfg] jtag_ntrst_assert_width 10 reset_config trst_only Add this to openocd/tcl/target as longan.cfg: # script for Longan nano # # longan nano devices support JTAG # transport select jtag if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME riscv } set ...