HRRZI C(AC) <- 0,,E

 Bluepills Its no surprise that Bluepills, such as they were, a smoking sub $2 deal would dry up eventually, taken over by clones, some subtle, some overt. With supply issues still plaguing ST parts for hobbyists, what about these cheap Chinese clone parts? Lets dive into the Air32F103. Air32F103 I bought 5 of these $1.90 boards. They look like this: Some notables vs a stock bluepill: 1) Castellated pins with flat underside for use as a module 2) 3 LEDs R/G/B (vs just the G for a bluepill) 3) Clone of ST's peripherals 4) over clockable to 256Mhz (spec is 216Mhz) (original STM32F103CB is 72Mhz) 5) 32K of ram. But, via secret regs, 97K(!) 6) top and bottom debug pads, top for JLINK, bottom, legacy STLINK SWD 7) USB C vs USB mini 8) BOOT as a button vs jumper 9) 2 12bit DACs (STM32F103CB's don't have that) 10) QSPI (hidden support) 11) Undocumented crypto block from MegaHunt (includes: AES/DES/3DES/SHA/SM[1,3,4,7]) Clocking As mentioned 256Mhz is possible. One Q is how do they...

  The GD32VF103 This chip is a peripheral clone of an STM32F103. The CPU is swapped out for a Risc-V. Openocd debug using JTAG Using the release on github: https://github.com/riscv/riscv-openocd Build it: ./bootstrap  ./configure --enable-ftdi --enable-stlink --enable-ti-icdi --enable-jlink --enable-cmsis-dap --enable-xds110 make   We can connect to the target. Wiring to a J-Link is as so: ARM20 JTAG: Pin1 VCC -> 3V3 Pin3 TRST -> RESET Pin5 TDI -> JTDI (underside of board) Pin7 TMS -> JTMS Pin9 TCLK -> JTCLK Pin13 TDO -> JTDO Add this to openocd/tcl/board as bluepillGDF103.cfg adapter speed 8000 source [find interface/jlink.cfg] source [find target/longan.cfg] jtag_ntrst_assert_width 10 reset_config trst_only Add this to openocd/tcl/target as longan.cfg: # script for Longan nano # # longan nano devices support JTAG # transport select jtag if { [info exists CHIPNAME] } {    set _CHIPNAME $CHIPNAME } else {    set _CHIPNAME riscv } set ...