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 The GD32VF103

This chip is a peripheral clone of an STM32F103. The CPU is swapped out for a Risc-V.




Openocd debug using JTAG

Using the release on github:
https://github.com/riscv/riscv-openocd
Build it:
./bootstrap 
./configure --enable-ftdi --enable-stlink --enable-ti-icdi --enable-jlink --enable-cmsis-dap --enable-xds110
make
 
We can connect to the target.

Wiring to a J-Link is as so:

ARM20 JTAG:
Pin1 VCC -> 3V3
Pin3 TRST -> RESET
Pin5 TDI -> JTDI (underside of board)
Pin7 TMS -> JTMS
Pin9 TCLK -> JTCLK
Pin13 TDO -> JTDO

Add this to openocd/tcl/board as bluepillGDF103.cfg

adapter speed 8000
source [find interface/jlink.cfg]
source [find target/longan.cfg]
jtag_ntrst_assert_width 10
reset_config trst_only

Add this to openocd/tcl/target as longan.cfg:

# script for Longan nano

#
# longan nano devices support JTAG
#
transport select jtag

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME riscv
}

set _ENDIAN little

if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x1000563D
}

jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_DAP_TAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0

# Work-area is a space in RAM used for flash programming
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x5000
}

# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
    set _FLASH_SIZE $FLASH_SIZE
} else {
    # autodetect size
    set _FLASH_SIZE 0
}

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash

#flash bank $_FLASHNAME gd32vf103 0x08000000 0 0 0 $_TARGETNAME
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
riscv set_reset_timeout_sec 1
init

halt


Run openocd:
root@ubuntu:/p4work/riscv-openocd/tcl# ../src/openocd -f board/bluepillGDF103.cfg
Open On-Chip Debugger 0.11.0+dev-02415-gfad123a (2022-10-29-17:33)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : J-Link ARM V8 compiled Dec  1 2009 11:42:48
Info : Hardware version: 8.00
Info : VTarget = 3.339 V
Info : clock speed 8000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x1000563d (mfg: 0x31e (Andes Technology Corporation), part: 0x0005, ver: 0x1)
Info : JTAG tap: auto0.tap tap/device found: 0x790007a3 (mfg: 0x3d1 (GigaDevice Semiconductor (Beijing) Inc), part: 0x9000, ver: 0x7)
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 5 -expected-id 0x790007a3"
Info : [riscv.cpu] datacount=4 progbufsize=2
Error: [riscv.cpu] Hart doesn't exist.
Error: [riscv.cpu] Hart is not halted!
Info : [riscv.cpu] Examined RISC-V core; found -1 harts
Info : [riscv.cpu]  XLEN=32, misa=0x40901105
[riscv.cpu] Target successfully examined.
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
trst_only separate trst_push_pull

Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections

Not sure what the Hart not existing messages are about. Hardware Thread is my understanding of what a Hart is. No matter, GDB can attach, and reset the target. Note that the Risc-V came from Andes Technology. This is a TW IP provider, GigaDevice semi just does the integration with 'their' peripherals. Curious how they copied ST's peripherals, there is a lot in those peripherals so it would be a real job to make a workalike.

Flash programmed from openocd

Seems to work:

(gdb) load
Loading section .text, size 0x12b4 lma 0x50000
Loading section .rodata, size 0x1bc lma 0x512b4
Loading section .eh_frame, size 0x3c lma 0x51470
Loading section .sdata, size 0x3b lma 0x514ac
Start address 0x00050000, load size 5351
Transfer rate: 6 KB/sec, 1337 bytes/write.
(gdb) x/32x 0
0x0: 0xfffb1197 0x80018193 0xfffb1117 0xa5810113
0x10: 0x00001517 0x49c50513 0xfffb0597 0xfe858593
0x20: 0xfffb0617 0x01b60613 0x00c5fa63 0x00052283
0x30: 0x0055a023 0x05910511 0xfec5eae3 0xfffb0517

UART

Good old UART works. Hold reset then hold boot0 release in same order.
Connect a USB to UART adapter to the board. VCC -> 5V pin, GND to GND, Green wire to R0, White to T0. (at least those are the colours on my Adafruit adapter).

Ubuntu can install stm32flash. Then, a raw binary (the -f flag) programs the FW. Watch out with /dev/ttyUSB0, by default its root owned so stm32flash may fail.

stm32flash -g 0x08000000 -b 115200 -w firmware.bin -f /dev/ttyUSB0

Software

Using Fabien Chouteau's PicoRV32 example code. Its Ada Zero Footprint. Linked at 0. 


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