Mips-X Mips-X as described earlier on the blog was a Stanford University grad project. A 32bit RISC CPU with some unique features for one, it had 2 delay slots for control change instructions, branches and jumps. I am not aware of any other processor that has that. We had a visit from John Hennessy (Stanford Mips project faculty lead and ultimately university president) one day (not Mips-X related) and I asked him, "why two delay slots?" his paraphrased answer was "It was a graduate project, we were just trying things out". The Shifter Mips-X had a barrel shifter and exposed it to the programmer via these opcodes: asr rSRC,rDST,#1..32 rotlb rSRC1,rSRC2,rDST rotlcb rSRC1,rSRC2,rDST sh rSRC1,rSRC2,rDST,#1..32 Via a combination of the above, all the needed shift operations could be done. Observe though there is no variable shift , just fixed # shift values. My Shift function Now here is a good puzzle for the reader to parse my varia...